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NB4N11M 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator
Description
T h e N B 4 N 11 M i s a d i f f e r e n t i a l 1 -t o -2 c l o c k / d a t a distribution/translation chip with CML output structure, targeted for high-speed clock/data applications. The device is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device produces two identical differential output copies of clock or data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such, NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 5). The CML outputs are 16 mA open collector (See Figure 18) which requires resistor (RL) load path to VTT termination voltage. The open collector CML outputs must be terminated to VTT at power up. Differential outputs produces current-mode logic (CML) compatible levels when receiver loaded with 50 W or 25 W loads connected to 1.8 V, 2.5 V or 3.3 V supplies (see Figure 19). This simplifies device interface by eliminating a need for coupling capacitors. The device is offered in a small 8-pin TSSOP package. Application notes, models, and support documentation are available at www.onsemi.com.
Features
http://onsemi.com MARKING DIAGRAM*
8 1 TSSOP-8 DT SUFFIX CASE 948R 8 E11M ALYWG G
1
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q0 Q0 D D Q1 Q1
* * * * * * * * *
Maximum Input Clock Frequency > 2.5 GHz Maximum Input Data Rate > 2.5 Gb/s Typically 1 ps of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, RL = 25 W 420 ps Typical Propagation Delay 150 ps Typical Rise and Fall Times Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and VTT = 1.8 V to 3.6 V Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices These are Pb-Free Devices*
Figure 1. Functional Block Diagram ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
November, 2005 - Rev. 1
1
Publication Order Number: NB4N11M/D
NB4N11M
Q0
1
8
VCC
Q0
2
7
D
Q1
3
6
D
Q1
4
5
VEE
Figure 2. Pinout (Top View) and Logic Diagram
Table 1. Pin Description
Pin 1 Name Q0 I/O CML Output Description Noninverted differential output. Typically receiver terminated with 50 W resistor to VTT. Open collector CML outputs must be terminated to VTT at powerup. Inverted differential output. Typically receiver terminated with 50 W resistor to VTT. Open collector CML outputs must be terminated to VTT at powerup. Noninverted differential output. Typically receiver terminated with 50 W resistor to VTT. Open collector CML outputs must be terminated to VTT at powerup. Inverted differential output. Typically receiver terminated with 50 W resistor to VTT. Open collector CML outputs must be terminated to VTT at powerup. Negative supply voltage. Inverted differential input. Noninverted differential input. Positive supply voltage.
2 3
Q0 Q1
CML Output CML Output
4 5 6 7 8
Q1 VEE D D VCC
CML Output - LVPECL, CML, HSTL, LVCMOS, LVDS, LVTTL Input LVPECL, CML, HSTL, LVCMOS, LVDS, LVTTL Input -
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Table 2. ATTRIBUTES
Characteristics ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Human Body Model Machine Model 8-TSSOP Oxygen Index: 28 to 34 Value > 1000 V > 70 V Level 1 UL 94 V-0 @ 0.125 in 197
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI VO TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Output Voltage Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 2) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm 1S2P (Note 2) < 3 Sec @ 260C TSSOP-8 TSSOP-8 TSSOP-8 Minimum Maximum Condition 1 VEE = -0.5 V VCC = +0.5 V VEE = 0 V VCC = 0 V VI = VCC +0.4 V VI = VEE -0.4 V Condition 2 Rating 4 -4 4 -4 VEE + 600 VCC + 400 -40 to +85 -65 to +150 190 130 41 to 44 265 Unit V V V V mV mV C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 2. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs VCC = 3.0 V to 3.6 V, VEE = 0 V, TA = -40C to +85C
Symbol ICC VOH VOL |VOD| VOH VOL |VOD| VOH VOL |VOD| VOH VOL |VOD| Vth VIH VIL VIHD VILD VCMR |VID| CIN Characteristic Power Supply Current (Inputs and Outputs Open) Min Typ 25 Max 35 Unit mA
RL = 50 W, VTT = 3.6 V to 2.5 V Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Differential Output Voltage Magnitude VTT - 60 VTT - 1100 640 VTT - 10 VTT - 800 780 VTT VTT - 640 1000 mV mV mV
RL = 25 W, VTT = 3.6 V to 2.5 V $5% Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Differential Output Voltage Magnitude VTT - 60 VTT - 550 320 VTT - 10 VTT - 400 390 VTT VTT - 320 500 mV mV mV
RL = 50 W, VTT = 1.8 V $5% Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Differential Output Voltage Magnitude VTT - 170 VTT - 1100 570 VTT - 10 VTT - 800 780 VTT VTT - 640 1000 mV mV mV
RL = 25 W, VTT = 1.8 V $5% Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Differential Output Voltage Magnitude VTT - 85 VTT - 500 285 VTT - 10 VTT - 400 390 VTT VTT - 320 500 mV mV mV
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 14 and 16) Input Threshold Reference Voltage Range (Note 5) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage VEE Vth + 100 VEE - 400 VEE VEE - 400 VEE 100 1.5 VCC VCC + 400 Vth - 100 VCC + 400 VCC - 100 VCC VCC - VEE mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15 and 17) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) Differential Input Voltage Magnitude (|VIHD - VILD|) (Note 7) Input Capacitance (Note 7) mV mV mV mV pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. CML outputs require RL receiver termination resistors to VTT for proper operation. Outputs must be connected through RL to VTT at power up. The output parameters vary 1:1 with VTT. 4. Input parameters vary 1:1 with VCC. 5. Vth is applied to the complementary input when operating in single-ended mode. 6. VCMR (MIN) varies 1:1 with VEE, VCMR max varies 1:1 with VCC. 7. Parameter guaranteed by design and evaluation but not tested in production.
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Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, VEE = 0 V; (Note 8)
-40C Symbol VOUTPP Characteristic Output Voltage Amplitude (RL = 50 W) fin 1 GHz (See Figure 12) fin 1.5 GHz fin 2.5GHz Output Voltage Amplitude (RL = 25 W) fin 1 GHz (See Figure 12) fin 1.5 GHz fin 2.5GHz Maximum Operating Data Rate Propagation Delay to Output Differential @ 0.5 GHz Duty Cycle Skew (Note 9) Within Device Skew Device to Device Skew (Note 13) RMS Random Clock Jitter RL = 50 W and RL = 25 W (Note 11) fin = 750 MHz fin = 1.5 GHz fin = 2.5 GHz Peak-to-Peak Data Dependent Jitter RL = 50 W fDATA = 1.5 Gb/s (Note 12) fDATA = 2.5 Gb/s Peak-to-Peak Data Dependent Jitter RL = 25 W fDATA = 1.5 Gb/s (Note 12) fDATA = 2.5 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 10) Output Rise/Fall Times @ 0.5 GHz (20% - 80%) Q, Q 100 150 300 Min 550 400 150 280 280 100 1.5 300 Typ 660 640 400 370 360 300 2.5 420 2 5 20 1 1 1 15 20 5 10 600 20 25 100 3 3 3 55 85 35 35 100 150 300 Max Min 550 400 150 280 280 100 1.5 300 25C Typ 660 640 400 370 360 400 2.5 420 2 5 20 1 1 1 15 20 5 10 600 20 25 100 3 3 3 55 85 35 35 100 150 300 Max Min 550 400 150 280 280 100 1.5 300 85C Typ 660 640 400 370 360 400 2.5 420 2 5 20 1 1 1 15 20 5 10 600 20 25 100 3 3 3 55 85 35 35 mV ps Max Unit mV
VOUTPP
mV
fDATA tPLH, tPHL tSKEW
Gb/s ps ps
tJITTER
ps
VINPP tr tf
OUTPUT VOLTAGE AMPLITUDE (mV)
700 600 500 400 300 200 100 0 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 RL = 25 W RL = 50 W
OUTPUT VOLTAGE AMPLITUDE (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All output loaded with an external RL = 50 W and RL = 25 W to VTT. Outputs must be connected through RL to VTT at power up. Input edge rates 150 ps (20% - 80%). 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 0.5 GHz. 10. VINPP (MAX) cannot exceed VCC - VEE. Input voltage swing is a single-ended measurement operating in differential mode. 11. Additive RMS jitter with 50% duty cycle clock signal. 12. Additive peak-to-peak data dependent jitter with input NRZ data signal (PRBS 223-1). 13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 800 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 RL = 25 W RL = 50 W
INPUT CLOCK FREQUENCY (GHz) (VCC - VEE = 3.3 V VTT = 3.3 V @ 255C Vin = 100 mV)
INPUT CLOCK FREQUENCY (GHz) (VCC - VEE = 3.0 V VTT = 1.71 V @255C Vin = 100 mV)
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) at Ambient Temperature (Typical)
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NB4N11M
80 70 60 TIME (ps) TIME (ps) 50 40 30 20 10 0 0.5 0.75 1 1.25 1.5 1.75 2 85C 25C -40C 35 30 25 20 15 10 5 0 0.5 0.75 1 1.25 1.5 1.75 2 -40C 85C
25C
2.25 2.5 2.75 3
2.25 2.5 2.75 3
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Data Dependent Jitter vs. Frequency and Temperature (VCC - VEE = 3.3 V; VTT = 3.3 V @ 255C; VIN = 100 mV; PRBS 223-1; RL = 50 W)
600 550 500 TIME (ps) 450 400 350 300 -40 TIME (ps) tPD 600 550 500 450 400 350
Figure 5. Data Dependent Jitter vs. Frequency and Temperature (VCC - VEE = 3.3 V; VTT = 3.3 V @ 255C; VIN = 100 mV; PRBS 223-1; RL = 25 W)
tPD
25 TEMPERATURE (C)
85
300 VEE - 0.5 V
V CC * V EE 2 INPUT OFFSET VOLTAGE (V)
VCC + 0.5 V
Figure 6. Typical Propagation Delay vs. Temperature (VCC - VEE = 3.3 V; VTT = 3.3 V @ 255C; Vin = 100 mV; RL = 50 W)
Figure 7. Typical Propagation Delay vs. Input Offset Voltage (VCC - VEE = 3.3 V; VTT = 3.3 V @ 255C; Vin = 100 mV RL = 50 W)
35 30 CURRENT (mA) 25 20 15 10 5 0 -40 25 TEMPERATURE (C) 85 ICC
Figure 8. Supply Current vs. Temperature http://onsemi.com
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VOLTAGE (200 mV/div)
DDJ = 5 ps
VOLTAGE (100 mV/div)
DDJ = 3 ps
TIME (266.8 ps/div)
TIME (266.8 ps/div)
Figure 9. Typical Differential Output Waveform at 750 Mb/s (RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 24 ps)
VOLTAGE (200 mV/div)
VOLTAGE (100 mV/div)
DDJ = 12 ps
DDJ = 5 ps
TIME (133.2 ps/div)
TIME (133.2 ps/div)
Figure 10. Typical Differential Output Waveform 1.5 Gb/s (RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 25 ps)
VOLTAGE (200 mV/div)
DDJ = 20 ps
VOLTAGE (100 mV/div)
DDJ = 7 ps
TIME (80 ps/div)
TIME (80 ps/div)
Figure 11. Typical Differential Output Waveform 2.5 Gb/s (RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 24 ps)
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D VINPP = VIH(D) - VIL(D) D Q Q tPLH VOUTPP = VOH(Q) - VOL(Q) tPHL
Figure 12. AC Reference Measurement
VTT
50 W DUT Driver Device Q Z = 50 W Q Z = 50 W
50 W D Receiver Device D
Figure 13. Typical Termination for Output Driver and Device Evaluation
D Vth Vth D
D
D
Figure 14. Differential Input Driven Single-Ended
Figure 15. Differential Inputs Driven Differentially
VCC Vthmax
VIHmax VILmax D VIH Vth VIL VIHmin VILmin
VCC VCMmax D VCMR D VCMmax GND
VIHCLKmax VILCLKmax VID = VIHD - VILD VIHDtyp VILDtyp VIHDmin VILDmin
Vth
Vthmin GND
Figure 16. Vth Diagram
Figure 17. VCMR Diagram
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VCC
Input ESD D
1.25 kW 1.25 kW
RC
RC
1.25 kW 1.25 kW
Input ESD D IN
Q Q
IN Input ESD Internal Current Source Input ESD 16 mA Current Source
VEE Input
VEE Output
Figure 18. CML Input and Output Structure
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VTTA = VCCA
VCC = 3.3 V Z = 50 W NB4N11M VTTB = VCCB 50 W 50 W Z = 50 W
VCCA = 1.8 V 2.5 V or 3.3 V 50 W 50 W Receiver A VTTB = VCCB Z = 50 W 50 W Z = 50 W Receiver B 50 W
VCCB = 1.8 V 2.5 V or 3.3 V
VEE = 0 V
VTTC = VCCC
VCC = 3.3 V Z = 75 W NB4N11M Z = 75 W
VCCC = 1.8 V 2.5 V or 3.3 V 75 W 75 W Receiver C VTTD = VCCD Z = 100 W 100 W Z = 100 W Receiver D 100 W
VCCD = 1.8 V 2.5 V or 3.3 V
VEE = 0 V
Figure 19. Typical Examples of the Application Interface
ORDERING INFORMATION
Device NB4N11MDTG NB4N11MDTR2G Package TSSOP-8 (Pb-Free) TSSOP-8 (Pb-Free) Shipping 100 Units / Rail 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8 1
5
L
PIN 1 IDENT
4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
G DETAIL E
-W-
DIM A B C D F G K L M
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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